1. Field of the Invention
This invention relates generally to the field of semiconductor processing. More particularly, this invention relates to a method for dopant deposition and oxidation in the semiconductor manufacturing process.
2. Background of the Invention
In semiconductor processing, when the load size is increased in an attempt to get a greater number of semiconductor wafers out of a single process run, a number of problems are encountered. In a dopant deposition and oxidation process, load and radial silicon resistance uniformity of resulting semiconductor wafers is of great concern.
For example, in a conventional semiconductor manufacturing environment, a relatively small number of wafers (e.g. 100 or less) are processed during deposition. When a dopant glass is generated as part of this process, the temperature of a chamber containing the wafers is generally brought up to about 950.degree. C. after which a dopant vapor (e.g. POCl.sub.3 - phosphorus oxychloride) is generally introduced into the chamber by a carrier gas (N.sub.2) at a rate of approximately 225 sccm through a bubbler containing liquid POCl.sub.3 at about 25.degree. C. The results of such a process for a relatively small number of wafers is generally acceptable. A test batch produced a resistance variation in the silicon resistance Rs of approximately 3.5% across a single wafer and 3.3% being a typical variation across the load of wafers in one test batch.
Unfortunately, when the size of the batch is increased, the variation in resistance increases substantially resulting in a less predictable process with less predictable circuit performance. In tests conducted using the same process as above and simply increasing the number of wafers used to 250, this resistance variation across a single wafer increased to approximately 27.5% with the variation across the load of wafers of approximately 24.2%. This degradation in variation across a single wafer is thought to be a result of changes in gas flow with the portions of some wafers being exposed to more of the dopant gas than others by virtue of their location within the chamber. For example, some of the wafers will be located adjacent the ports through which the gas is introduced into the chamber, while others are farther away. Also, the distance between wafers is reduced when the load size is increased from 50 to 250. Those located closer to the dopant gas source and the heat source will have exposure to higher concentrations of dopant which are driven into the semiconductor for a somewhat longer period of time.
Another problem with known processes is that the dopant deposition and immediately subsequent dopant diffusion/oxidization oxidization steps are carried out using two separate furnace cycles. This increases handling and potential damage as well as production time, cost and complexity.
In U.S. Pat. No. 4,588,454 to Khadder et al., the dopant introduction phase of semiconductor processing is carried out by a multiple step process. First, an approximately 1000 .ANG. thick layer of Boron doped glass is deposited on the wafer at a relatively low temperature by introducing a Boron gas (BCl.sub.3) in the presence of steam to rapidly (estimated to be approximately 10 to 20 minutes) form a thick layer of Boron doped glass. The dopant is then driven into the semiconductor wafer by ramping up the temperature to drive the Boron from the dopant glass into the wafer. The glass is then etched away prior to a diffusion at an elevated temperature. Two separate furnace cycles with an intermediate etch for dopant glass removal are used in this process.